On Fault Modeling and Testing of Content-addressable Memories

Associative or content addressable memories can be used for many computing applications. This paper discusses fault modeling for the content addressable memory (CAM) chips. Detailed examination of a single CAM cell is presented. A functional fault model for a CAM architecture executing exact match derived from the single cell model is presented. An efficient testing strategy can be derived using the proposed fault mode

Faulty Behavior of Storage Elements and Its Effects on Sequential Circuits

It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here. A more accurate higher level fault model for elementary SEs that better represents the physical failures is presented. It is shown that a minimal (stuck-at) model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SEs that are not covered by the minimal fault model. These include data-feedthrough and clock-feedthrough behaviors, as well as problems with logic level retention. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit. The detectability of feedthrough faults is considered

Data-Feedthrough Faults in Circuits using Unclocked Storage Elements

Some faults in storage elements (SEs) do not manifest as stuck-at-0/1 faults. These include data-feedthrough faults that cause the SE cell to exhibit combinational behaviour. The authors investigate the implications of such faults on the behaviour of circuits using unclocked SEs. It is shown that effects of data-feedthrough faults at the behavioural level are different from those due to stuck-at faults, and therefore tests generated for the latter may be inadequat

Association between age at disease onset of anti-neutrophil cytoplasmic antibody-associated vasculitis and clinical presentation and short-term outcomes

Objectives: ANCA-associated vasculitis (AAV) can affect all age groups. We aimed to show that differences in disease presentation and 6 month outcome between younger- A nd older-onset patients are still incompletely understood. Methods: We included patients enrolled in the Diagnostic and Classification Criteria for Primary Systemic Vasculitis (DCVAS) study between October 2010 and January 2017 with a diagnosis of AAV. We divided the population according to age at diagnosis: <65 years or ≥65 years. We adjusted associations for the type of AAV and the type of ANCA (anti-MPO, anti-PR3 or negative). Results: A total of 1338 patients with AAV were included: 66% had disease onset at <65 years of age [female 50%; mean age 48.4 years (s.d. 12.6)] and 34% had disease onset at ≥65 years [female 54%; mean age 73.6 years (s.d. 6)]. ANCA (MPO) positivity was more frequent in the older group (48% vs 27%; P = 0.001). Younger patients had higher rates of musculoskeletal, cutaneous and ENT manifestations compared with older patients. Systemic, neurologic,cardiovascular involvement and worsening renal function were more frequent in the older-onset group. Damage accrual, measured with the Vasculitis Damage Index (VDI), was significantly higher in older patients, 12% of whom had a 6 month VDI ≥5, compared with 7% of younger patients (P = 0.01). Older age was an independent risk factor for early death within 6 months from diagnosis [hazard ratio 2.06 (95% CI 1.07, 3.97); P = 0.03]. Conclusion: Within 6 months of diagnosis of AAV, patients >65 years of age display a different pattern of organ involvement and an increased risk of significant damage and mortality compared with younger patients

Modeling of Intra-Cell Defects in CMOS SRAM

The effect of defects within a single cell of a static random access memory (SRAM) is examined. All major types of faults, including bridging, transistor stuck-open and stuck-on, are examined. A significant fraction of all faults cause high IDDQ values to be observed. Faults leading to inter-cell coupling are identified

Differential I DDQ Testable Static RAM Architecture

A testable design that enhances the I DDQ testability of random access memories (SRAMs) for off-line testing is proposed. Increased accuracy and test speed can be achieved by memory array partitioning. Comaparision of I DDQ values from two blocks is performed during parallel write/read operations to memory locations of the two blocks. Simultaneous write/read operations to all locations within physically interleaved block can significantly enhance the test speed as well as fault activation. 1 Introduction With the increasing complexity of semiconductor memories, the nature of the failure modes have become more complex and subtle [1, 2]. Failure modes such as gate-oxide shorts, bridging defects, parasitic transistor leakage, defective p-n junctions, and transistors with incorrect threshold voltages, do not affect the logical behavior. Such faults may pass the functional and logical testing, but may malfunction overtime, causing reliability hazards. Many of those faults cause elevated qu..